Complementary metal oxide semiconductor (CMOS) device having gate structures connected by a metal gate conductor

摘要

A complementary metal oxide semiconductor (CMOS) device including a substrate including a first active region and a second active region, wherein each of the first active region and second active region of the substrate are separated by from one another by an isolation region. A n-type semiconductor device is present on the first active region of the substrate, in which the n-type semiconductor device includes a first portion of a gate structure. A p-type semiconductor device is present on the second active region of the substrate, in which the p-type semiconductor device includes a second portion of the gate structure. A connecting gate portion provides electrical connectivity between the first portion of the gate structure and the second portion of the gate structure. Electrical contact to the connecting gate portion is over the isolation region, and is not over the first active region and/or the second active region.

主权项

1. A method of forming a CMOS device, said method comprising:
forming at least one isolation region in a semiconductor substrate to provide at least one first active region and at least one second active region; forming a gate structure extending across said at least one isolation region and spanning from said at least one first active region to said at least one second active region, wherein said gate structure includes at least one gate dielectric layer, at least one gate conductor layer, and at least one dielectric cap layer; forming a first source region and a first drain region of a first conductivity type on opposing sides of said gate structure in said at least one first active region, and a second source region and a second drain region of a second conductivity type on opposing sides of said gate structure in said at least one second active region; forming an opening in a portion of said at least one dielectric cap layer to expose a contact portion of said at least one gate conductor layer over said at least one isolation region, wherein a remaining portion of said at least one dielectric cap layer is present over said at least one first active region and said at least one second active region; and forming an interconnect in direct contact with said contact portion of said at least one gate conductor layer.