Independent control of processor core retention states

摘要

In an embodiment, a processor includes a first processor core, a second processor core, a first voltage regulator to provide a first voltage to the first processor core with a first active value when the first processor core is active, and a second voltage regulator to provide a second voltage to the second processor core with a second active value when the second processor core is active. Responsive to a request to place the first processor core in a first low power state with an associated first low power voltage value, the first voltage regulator is to reduce the first voltage to a second low power voltage value that is less than the first low power voltage value, independent of the second voltage regulator. First data stored in a first register of the first processor core is retained at the second low power value. Other embodiments are described and claimed.

主权项

1. A processor comprising:
a first processor core; a second processor core; a first voltage regulator to provide a first voltage to the first processor core, the first voltage having a first active value when the first processor core is active; and a second voltage regulator to provide a second voltage to the second processor core, the second voltage having a second active value when the second processor core is active; wherein responsive to a first request to place the first processor core in a first low power state with an associated first low power voltage value that is less than the first active value, the first voltage regulator is to program the first voltage to a first retention voltage value based on first retention voltage information obtained from a storage, wherein the first retention voltage value is less than the first low power voltage value, and first data stored in a first register of the first processor core is to be retained while the first voltage is at the first retention voltage value.