Semiconductor device and electronic device

摘要

A semiconductor device includes a clock input circuit that receives an external clock signal, a PLL circuit for input timing control that performs phase adjustment between the external clock signal and a delayed clock signal to generate an internal clock signal used to acquire input data, and a delay circuit that delays the internal clock signal to output the internal clock signal that is delayed to a PLL circuit for input timing control as a delayed clock signal. The semiconductor device further includes a PLL circuit for output timing control that performs phase adjustment between the external clock signal and a delayed clock signal to generate an internal clock signal used to output output data, and a delay circuit that delays the internal clock signal to output the internal clock signal that is delayed to the PLL circuit for output timing control as a delayed clock signal.

主权项

1. A semiconductor device comprising a communication controller, the communication controller comprising:
(a) a clock input circuit that receives an external clock signal; (b) a first PLL circuit that performs phase adjustment between the external clock signal and a first delay clock signal to generate a first internal clock signal used to acquire input data; (c) a first delay circuit that delays a first feedback signal outputted from the first PLL circuit to thereby generate the first clock signal, and outputs the first delay clock signal to the first PLL circuit; (d) a second PLL circuit that performs phase adjustment between the external clock signal and a second delay clock signal to generate a second internal clock signal used to output output data; and (e) a second delay circuit that delays a second feedback signal outputted from the second PLL circuit to thereby generate the second clock signal, and outputs the second delay clock signal to the second PLL circuit.