Growth of multi-layer group III-nitride buffers on large-area silicon substrates and other substrates

摘要

A method includes forming a first epitaxial layer over a semiconductor substrate and etching the first epitaxial layer to form multiple separated first epitaxial regions. The method also includes forming a second epitaxial layer over the etched first epitaxial layer. Each epitaxial layer includes at least one Group III-nitride, and the epitaxial layers collectively form a buffer. The method further includes forming a device layer over the buffer and fabricating a semiconductor device using the device layer. The second epitaxial layer could include second epitaxial regions substantially only on the first epitaxial regions. The second epitaxial layer could also cover the first epitaxial regions and the substrate, and the second epitaxial layer may or may not be etched. The device layer could be formed during the same operation used to form the second epitaxial layer.

主权项

1. A method comprising:
providing a semiconductor substrate comprised of a material selected from the group of silicon, sapphire, or silicon carbide; forming a nucleation layer over the substrate wherein, the nucleation layer is composed of aluminum nitride; forming a buffer layer over the nucleation layer, comprising a plurality of separated first epitaxial regions wherein, the plurality of separated first epitaxial regions form isolated component islands wherein, the component islands are configured to provide a starting surface structured to minimize dislocations; forming a second epitaxial layer directly on the first epitaxial layer, each of the epitaxial layers comprising at least one Group III-nitride, the first and second epitaxial layers collectively forming the buffer, wherein the buffer is comprised of multiple separated buffer regions of the first epitaxial layer and the second epitaxial layer; forming a device layer or portion of the device layer in which at least part of a semiconductor device is formed, wherein the device layer is selected from an individual layer or as part of another layer; doping the portion of the device layer with one or more dopants to form a source, a drain, or other transistor regions; and forming one or more conductive layers over the transistor region, patterning and etching to form source and drain contacts.