Positive edge flip-flop with dual-port slave latch

摘要

In an embodiment of the invention, a flip-flop circuit contains a first inverter, a pass gate, master latch, a transfer gate and a slave latch. The clock signals and retention control signals determine when the master latch is latched. The slave latch is configured to receive the output of the master latch, a second data bit D2, the clock signals, the retain control signals, the slave control signals. The clock signals, the retain control signals, and the slave control signals determine whether the output of the master latch or the second data bit D2 is latched in the slave latch. The retain control signals determine when data is stored in the slave latch during retention mode.

主权项

1. A flip-flop circuit comprising:
a first inverter configured to receive a first data bit and output a binary logical compliment of the first data bit; a pass gate configured to transfer the binary logical compliment of the first data bit to a master latch when a first clock signal is a logical low value and a second clock signal is a logical high value and wherein the pass gate is configured to not transfer the binary logical compliment of the first data bit to the master latch when the first clock signal is a logical high value and the second clock signal is a logical low value; the master latch configured to receive the binary logical compliment of the first data bit, the first clock signal, the second clock signal , a first retain control signal and a second retain control signal, wherein the first clock signal, the second clock signal, the first retain control signal, and the second retain control signal determine when a binary logical value of the first data bit is presented on a data output of the master latch and when the data output of the master latch is latched in the master latch; a transfer gate wherein the transfer gate transfers data from the data output of the master latch to an output of the transfer gate when the first clock signal transitions from a low logical value to a logical high value; a slave latch configured to receive the output of the transfer gate, a second data bit, the first clock signal, the second clock signal, the first retain control signal, the second retain control signal, a first slave control signal and a second slave control signal wherein the first clock signal, the second clock signal, the first retain control signal, the second retain control signal, the first slave control signal, and the second slave control signal determine whether the output of the transfer gate or the second data bit is latched in the slave latch.