Synchronous semiconductor memory device having delay locked loop circuit and method of controlling the delay locked loop circuit

摘要

An operating method of a delay locked loop (DLL) circuit for a semiconductor memory device is disclosed. The DLL circuit may include a plurality of sub-circuits. The method may include calculating an additive latency value based on predetermined parameters, and controlling a set of the plurality of sub-circuits of the DLL circuit to be maintained in a turn-off state based on the calculated additive latency value, during a period of time after the semiconductor device receives an operation command in a power saving mode.

主权项

1. An operating method of a delay locked loop (DLL) circuit for a semiconductor memory device, the DLL circuit including a plurality of sub-circuits, the method comprising:
calculating an additive latency value based on predetermined parameters; and controlling a set of the plurality of sub-circuits of the DLL circuit to be maintained in a turn-off state based on the calculated additive latency value, during a period of time after the semiconductor memory device receives an operation command in a power saving mode.