Non-volatile memory channel control using a general purpose programmable processor in combination with a low level programmable sequencer

摘要

A system includes a control processor, a non-volatile memory device interface, and a micro-sequencer. The control processor may be configured to receive commands and send responses via a command interface. The non-volatile memory device interface may be configured to couple the system to one or more non-volatile memory devices. The micro-sequencer is generally coupled to (i) the control processor and (ii) the non-volatile memory device interface. The micro-sequencer includes a control store readable by the micro-sequencer and writable by the control processor. In response to receiving a particular one of the commands, the control processor is enabled to cause the micro-sequencer to begin executing at a location in the control store according to the particular command and the micro-sequencer is enabled to perform at least a portion of the particular command according to a protocol of the one or more non-volatile memory devices coupled to the non-volatile memory device interface.

主权项

1. A system comprising:
a control processor configured to receive commands and send responses via a command interface; a non-volatile memory device interface configured to couple said system to one or more non-volatile memory devices; and a micro-sequencer coupled to (i) said control processor and (ii) said non-volatile memory device interface, said micro-sequencer comprising a control store readable by said micro-sequencer and writable by said control processor, wherein, in response to receiving a particular one of said commands,
said control processor is enabled to cause said micro-sequencer to begin executing at a location in the control store according to said particular one of said commands andsaid micro-sequencer is enabled to perform at least a portion of said particular one of said commands according to a protocol of said one or more non-volatile memory devices coupled to said non-volatile memory device interface.