| 发明名称 |
Memory matrix |
| 摘要 |
An integrated circuit comprises a memory matrix including: a first memory cell array; a first multiplexer (MUX) coupled to an input of the first memory cell array; a second MUX coupled to an output of the first memory cell array; a second memory cell array; a third MUX coupled to an input of the second memory cell array; and a fourth MUX coupled to an output of the second memory cell array. The second MUX is coupled to the fourth MUX. The fourth MUX is configured to pass a selected one of: (1) an output from the third MUX, (2) an output from the second memory cell array, or (3) an output from the second MUX. |
| 申请公布号 |
US9083340(B1) |
申请公布日期 |
2015.07.14 |
| 申请号 |
US201414278244 |
申请日期 |
2014.05.15 |
| 申请人 |
XILINX, INC. |
发明人 |
Wu Ephrem C.;Ji Hongbin;Camarota Rafael C. |
| 分类号 |
G06F7/38;H03K19/173;H03K19/177 |
主分类号 |
G06F7/38 |
| 代理机构 |
|
代理人 |
Chan Gerald |
| 主权项 |
1. An integrated circuit comprising a memory matrix, the memory matrix comprising:
a first memory cell array; a first multiplexer (MUX) coupled to an input of the first memory cell array; a second MUX coupled to an output of the first memory cell array; a second memory cell array; a third MUX coupled to an input of the second memory cell array; and a fourth MUX coupled to an output of the second memory cell array; wherein the second MUX is coupled to the fourth MUX, the fourth MUX configured to pass a selected one of: (1) an output from the third MUX, (2) an output from the second memory cell array, or (3) an output from the second MUX. |
| 地址 |
San Jose CA US |
