Vertical insulated-gate turn-off device having a planar gate

摘要

An insulated gate turn-off (IGTO) device has a layered structure including a p+ layer (e.g., a substrate), an n-type layer, a p-type layer (which may be a p-well), n+ regions formed in the surface of the p-type layer, and insulated planar gates over the p-type layer between the n+ regions. The layered structure forms vertical NPN and PNP transistors. The p-type layer forms the base of the NPN transistor. When the gates are sufficiently positively biased, the underlying p-type layer inverts to reduce the width of the base to increase the beta of the NPN transistor. This causes the product of the betas of the NPN and PNP transistors to exceed one, and the device becomes fully conductive. When the gate voltage is removed, the base width increases such that the product of the betas is less than one, and the device shuts off. No latch-up occurs in normal operation.

主权项

1. An insulated gate turn-off (IGTO) device formed as a die comprising:
a first semiconductor layer of a first conductivity type; a first electrode electrically contacting the first semiconductor layer; a second semiconductor layer of a second conductivity type over the first semiconductor layer; a third semiconductor layer of the first conductivity type over the second semiconductor layer; first regions of the second conductivity type formed in a top surface of the third semiconductor layer, adjacent first regions having a gap between them, wherein a vertical structure of NPN and PNP transistors is formed, and wherein the third semiconductor layer forms a first base of one of the transistors; a second electrode electrically contacting the first regions and the third semiconductor layer; and first planar gates above the gaps between the first regions and insulated from the third semiconductor layer, wherein the second electrode electrically contacts the adjacent first regions on opposite sides of the first planar gates, the third semiconductor layer having a thickness and a dopant concentration such that, when a forward biasing voltage is applied between the first electrode and the second electrode and when a turn-on voltage is applied to the gates, the gates create an inversion layer in the underlying third semiconductor layer to cause the first base to have a reduced width, causing the beta of the one of the transistors to increase beyond a first threshold to turn on the IGTO device to conduct a current between the first electrode and the second electrode, wherein, when a turn-off voltage is applied to the gates, the first base has an increased width, causing the beta of the one of the transistors to be reduced below a second threshold to turn off the IGTO device.