发明名称 Network communications processor architecture
摘要 Described embodiments provide a system having a plurality of processor cores and common memory in direct communication with the cores. A source processing core communicates with a task destination core by generating a task message for the task destination core. The task source core transmits the task message directly to a receiving processing core adjacent to the task source core. If the receiving processing core is not the task destination core, the receiving processing core passes the task message unchanged to a processing core adjacent the receiving processing core. If the receiving processing core is the task destination core, the task destination core processes the message.
申请公布号 US9081742(B2) 申请公布日期 2015.07.14
申请号 US201012782379 申请日期 2010.05.18
申请人 Intel Corporation 发明人 Sonnier David P.;Burroughs William G.;Vangati Narender R.;Mital Deepak;Munoz Robert J.
分类号 G06F15/167;H04L12/933;H04L12/931 主分类号 G06F15/167
代理机构 Nicholson De Vos Webster & Elliott LLP 代理人 Nicholson De Vos Webster & Elliott LLP
主权项 1. A system coupled to a network, the system comprising: a plurality of ring-coupled processing cores, the processing cores coupled by at least one ring bus; and a common memory adapted for direct communication with each of the processing cores, the common memory comprising a plurality of addressable memory arrays; at least one of the plurality of processing cores configured to generate one or more task messages corresponding to at least a portion of data packets received from the network; each processing core configured to: send a task message over the at least one ring bus to an adjacent processing core coupled to the ring bus, the task message having a corresponding one or more destination processing cores;check, upon receiving a task message, whether the processing core is a destination processing core for the task message and, if not, pass the task message unchanged to a next adjacent processing core coupled to the ring bus, whereby the task message is passed from the source processing core to each corresponding destination processing core on the ring bus;if the processing core is a destination engine for the task message, the processing core is configured to: read from the task message (i) an address of data in the common memory to be accessed by the destination processing core, and (ii) a flow identifier of the task;compute a hash value based on at least a part of the address; andselect, based on the computed hash value and the flow identifier of the task, one of the plurality of addressable memory arrays in which to store the received task; wherein, by having at least one of the processing cores receive a task message, execute a task, and provide a subsequent task message to a subsequent processing core based on the received data packet, a virtual pipeline is defined for processing the received data packet, the virtual pipeline defining a flow order for each task message through two or more of the plurality of processing cores, and wherein each task message comprises a field indicating one of the plurality of virtual pipelines through which the task message is processed.
地址 Santa Clara CA US