Method for reducing execution jitter in multi-core processors within an information handling system

摘要

A method of reducing execution jitter includes a processor having several cores and control logic that receives core configuration parameters. Control logic determines if a first set of cores are selected to be disabled. If none of the cores is selected to be disabled, the control logic determines if a second set of cores is selected to be jitter controlled. If the second set of cores is selected to be jitter controlled, the second set of cores is set to a first operating state. If the first set of cores is selected to be disabled, the control logic determines a second operating state for a third set of enabled cores. The control logic determines if the third set of enabled cores is jitter controlled, and if the third set of enabled cores is jitter controlled, the control logic sets the third set of enabled cores to the second operating state.

主权项

1. A computer implemented method of reducing execution jitter within a processor having a control logic and a plurality of individual cores, the method comprising:
receiving at least one core configuration parameter; determining from the at least one configuration parameter if a first set of one or more cores are selected to be disabled from operation; in response to none of the first set of cores being selected to be disabled, determining if a second set of one or more cores are selected to be jitter controlled; in response to the second set of the cores being selected to be jitter controlled, setting the second set of cores to a first operating state that reduces jitter; in response to the first set of cores being selected to be disabled, disabling the first set of cores and determining a second operating state that reduces jitter for a third set of one or more enabled cores; determining if the third set of enabled cores are selected to be jitter controlled; and in response to the third set of enabled cores being selected to be jitter controlled, setting the third set of enabled cores to the second operating state that reduces jitter.