Apparatuses and methods including memory array and data line architecture

摘要

Some embodiments include apparatus and methods having memory cells located in different device levels of a device, at least a portion of a transistor located in a substrate of the device, and a data line coupled to the transistor and the memory cells. The data line can be located between the transistor and the memory cells. Other embodiments including additional apparatus and methods are described.

主权项

1. A device comprising:
a first memory array located over a substrate; first data lines located between the substrate and the first memory array; a second memory array located over the substrate; second data lines located between the substrate and the second memory array; additional data lines located over the first and second memory arrays; a first circuit to selectively couple first memory cells of the first memory array to the additional data lines through at least a portion of the first data lines; and a second circuit to selectively couple second memory cells of the second memory array to the additional data lines through at least a portion of the second data lines, wherein at least a portion of each of the first and second circuit is located in the substrate.