N-CHANNEL AND P-CHANNEL END-TO-END FINFET CELL ARCHITECTURE WITH RELAXED GATE PITCH

摘要

A finFET block architecture uses end-to-end finFET blocks in which the fin lengths are at least twice the contact pitch, whereby there is enough space for interlayer connectors to be placed on the proximal end and the distal end of a given semiconductor fin, and on the gate element on the given semiconductor fin. A first set of semiconductor fins having a first conductivity type and a second set of semiconductor fins having a second conductivity type can be aligned end-to-end. Interlayer connectors can be aligned over corresponding semiconductor fins which connect to gate elements.

主权项

1. An integrated circuit, comprising:
a substrate; a first set of semiconductor fins aligned in a first direction on the substrate, one or more of the semiconductor fins in the first set including at least one channel region and at least two source/drain regions of finFETs; a second set of semiconductor fins aligned in the first direction on the substrate one or more of the semiconductor fins in the second set including at least one channel region and at least two source/drain regions of finFETs; a third set of semiconductor fins aligned in the first direction on the substrate, one or more of the semiconductor fins in the third set including at least one channel region and at least two source/drain regions of finFETs; a first power conductor over semiconductor fins in the first set and the third set between the first set and the third set; a patterned gate conductor layer including a plurality of gate elements on corresponding fins in the first and second sets of semiconductor fins, the gate elements being disposed over channel regions of the corresponding semiconductor fins; at least one patterned conductor layer overlying the patterned gate conductor layer; and a plurality of interlayer connectors, including interlayer connectors aligned over corresponding semiconductor fins in the first and second sets and connected to the gate elements of particular finFETs on the corresponding fins.