发明名称 AUTOMATIC SUB-MILLISECOND CLOCK SYNCHRONIZATION
摘要 According to one aspect, embodiments of the invention provide a system for monitoring a plurality of circuit branches coupled to an input line, the system comprising a communication bus, a controller having a primary clock with a first clock value and configured to sample voltage on the input line based on the first clock value, a plurality of sensor circuits, each sensor circuit having a secondary clock with a second clock value and configured to sample current in the at least one of the plurality of circuit branches based on the second clock value, and wherein the controller is further configured to initiate, via the communication bus, synchronization of at least one secondary clock and the primary clock, and to synchronize, via the communication bus, the at least one secondary clock and the primary clock to account for transmission latency in the communication bus.
申请公布号 WO2015102605(A1) 申请公布日期 2015.07.09
申请号 WO2013US78448 申请日期 2013.12.31
申请人 SCHNEIDER ELECTRIC IT CORPORATION 发明人 LINDER, STEPHEN, PAUL
分类号 G01R19/25 主分类号 G01R19/25
代理机构 代理人
主权项
地址