| 摘要 |
A receiver circuit includes: a parallelism portion; a sampling clock control portion; and a sampling clock generating portion. The parallelism portion generates a plurality of internal data by receiving a sampling clock signal and sampling a plurality of input data. The sampling clock control portion generates a delay control signal and a synchronizing completion signal by responding to the internal data and a clock signal of a first group. The sampling clock generating portion delays the clock signal of the first group and provides the clock signal of the first group as the sampling clock signal by responding to the delay control signal. The sampling clock generating portion provides a clock signal of a second group, a certain phase is faster than the clock signal of the first group, as the sampling clock signal by responding to the synchronizing completion signal. |
