发明名称 DATA PATTERN GENERATION FOR I/O TESTING
摘要 One feature pertains to a single data pattern being read from a pattern register located within a memory circuit or device. At least one of the plurality of data patterns is derived from the single data pattern, and the plurality of data patterns may be used in a test and sent to an output driver of the memory circuit. The plurality of data patterns may include a first data pattern and a second data pattern. The first data pattern may be derived from the single data pattern. The second data pattern is one of either a true copy of the single data pattern, an inverse copy of the single data pattern, an all zero bits data pattern, or an all one bits data pattern.
申请公布号 WO2015103289(A1) 申请公布日期 2015.07.09
申请号 WO2014US72795 申请日期 2014.12.30
申请人 QUALCOMM INCORPORATED 发明人 HOLLIS, TIMOTHY MOWRY
分类号 G11C29/02;G11C29/36 主分类号 G11C29/02
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