RESISTIVE MEMORY DEVICE CAPABLE OF IMPROVING SENSING MARGIN OF DATA

摘要

A resistive memory device includes a cell block having a plurality of unit memory cells in which a resistive element and a cell select element are connected to each other in series, the cell block operating in response to a word line, a bit line, and a source line, and a dummy line, when different interconnection layers form the source line and the bit line, respectively, connected to one of the interconnection layers which is formed at a lower side the remaining interconnection layer between the interconnection layers for the source line and the bit line, wherein the dummy line has a resistance lower than a resistance of the lower interconnection layer.

主权项

1. A resistive memory device comprising:
a cell block comprising a plurality of unit memory cells in which a resistive element and a cell select element are connected to each other in series, the cell block being configured to operate in response to a word line, a bit line, and a source line; and a dummy line, when different interconnection layers are configured to form the source line and the bit line, connected to one of the interconnection layers formed at a lower side of a remaining interconnection layer, the remaining interconnection layer being between the interconnection layers forming the source line and the bit line, wherein the dummy line has a lower resistance than a resistance of the lower interconnection layer.