START OF SEQUENCE DETECTION FOR ONE WIRE BUS

摘要

The disclosure relates to bus interface systems. In one embodiment, the bus interface system includes a bus line along with a master bus controller and a slave bus controller coupled to the bus line. In order to start a data frame, the master bus controller is configured to generate a sequence of data pulses along the bus line such that the sequence of data pulses is provided in accordance to a start of sequence (SOS) pulse pattern. The slave bus controller is configured to recognize that the sequence of data transmitted along the bus line by the master bus controller has been provided in accordance with the SOS pulse pattern. In this manner, the slave bus controller can detect when the master bus controller has started a new data frame. As such, the exchange of information through data frames can be synchronized along the bus line with requiring an additional bus line for a clock signal.

主权项

1. A bus interface system, comprising:
a bus line; a master bus controller coupled to the bus line, wherein the master bus controller is configured to generate a sequence of data pulses along the bus line such that the sequence of data pulses are provided in accordance to a first pulse pattern and the sequence of data pulses include a calibration data pulse; and a slave bus controller coupled to the bus line, wherein the slave bus controller comprises a decoder and the slave bus controller is configured to:
recognize that the sequence of data pulses transmitted along the bus line have been provided in accordance with the first pulse pattern; andcalibrate the decoder in accordance with the calibration data pulse in response to recognizing that the sequence of data pulses has been provided in accordance with the first pulse pattern.