发明名称 METHOD AND APPARATUS FOR ELECTRONIC SYSTEM MODEL GENERATION
摘要 A method of transmitting data is disclosed. At least one system block of a system-on-chip (SoC) is modeled at an untimed functional level in first and second untimed functional models. First and second transaction level (TL) models of the at least one system block system block are modeled at a transaction level (TL) using the first and second untimed functional models, respectively. First and second cycle accurate (CA) models are modeled at a cycle accurate (CA) level using the first and second TL models, respectively. Data is transmitted from the first untimed functional model to the first CA model, from the first CA model to the second CA model via a CA bus, and from the second CA model to the second untimed functional model.
申请公布号 US2015193568(A1) 申请公布日期 2015.07.09
申请号 US201514663476 申请日期 2015.03.20
申请人 TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. 发明人 MEHTA Ashok
分类号 G06F17/50 主分类号 G06F17/50
代理机构 代理人
主权项 1. A method comprising: generating an approximately timed (AT) model of a system block of a system-on-chip (SoC) at a transaction level (TL), wherein the AT model includes a four-phased communication including a start request, an end request, a start response, and an end response, the communication supporting non-blocking behavior; generating an untimed functional model of the system block at an untimed functional level, the untimed functional model configured to be invoked by the AT model; and generating a cycle accurate (CA) model of the system block at a cycle accurate (CA) level using the AT model.
地址 Hsin-Chu TW