发明名称 MICROARCHITECTURE FOR FLOATING POINT FUSED MULTIPLY-ADD WITH EXPONENT SCALING
摘要 Systems and methods for implementing a floating point fused multiply and accumulate with scaling (FMASc) operation. A floating point unit receives input multiplier, multiplicand, addend, and scaling factor operands. A multiplier block is configured to multiply mantissas of the multiplier and multiplicand to generate an intermediate product. Alignment logic is configured to pre-align the addend with the intermediate product based on the scaling factor and exponents of the addend, multiplier, and multiplicand, and accumulation logic is configured to add or subtract a mantissa of the pre-aligned addend with the intermediate product to obtain a result of the floating point unit. Normalization and rounding are performed on the result, avoiding rounding during intermediate stages.
申请公布号 EP2891056(A1) 申请公布日期 2015.07.08
申请号 EP20120787997 申请日期 2012.10.30
申请人 QUALCOMM INCORPORATED 发明人 WANG, LIANG-KAI
分类号 G06F7/483 主分类号 G06F7/483
代理机构 代理人
主权项
地址