发明名称 |
Active probe pod in logic analyzer |
摘要 |
An active probe pod (4) to be used with a logic analyzer (5) is disclosed. The active probe pod may be connected to the logic analyzer having a FPGA decoder (51) and to a DUT circuit board (1). The active probe pod may include a LVDS differential wire component (42) connectable to the FPGA decoder and a front-end circuit board (411) for capturing a weak signal input from the DUT circuit board. The front-end circuit board is adapted not to transmit the captured weak signal input over a long-distance signal transmission path, which helps minimize interferences with the weak signal input, while outputting a LVDS differential signal to the FPGA decoder for decoding. As the front-end circuit board is used for capturing the weak signal input, which falls within the category of one short-distance signal transmission, the signal reflection may not take place, without affecting the signal quality and/or attenuating the signal strength. |
申请公布号 |
EP2891890(A1) |
申请公布日期 |
2015.07.08 |
申请号 |
EP20140198832 |
申请日期 |
2014.12.18 |
申请人 |
ZEROPLUS TECHNOLOGY CO., LTD. |
发明人 |
CHENG, CHIU-HAO;TSAI, CHIH-MING |
分类号 |
G01R1/067;G01R31/319;G06F11/273 |
主分类号 |
G01R1/067 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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