| 摘要 |
<p>A purpose of this invention is to provide a novel pulse width controlled phase-locked loop circuit and the like that are capable of reducing phase shift. A solution of this invention is a phase-locked loop circuit which is controlled according to a pulse width of an input pulse signal. It includes a pulse width controlled oscillator that oscillates according to a pulse width of an input signal, a phase-frequency comparator that outputs the UP pulse signal or DN pulse signal according to the phase difference between the input pulse signal and an output signal of the pulse width controlled oscillator, and a pulse width integrator that generates an integration signal of the pulse signal according to the UP pulse signal and the DN pulse signal. The pulse width controlled oscillator oscillates according to the pulse width of the integration signal.</p> |
