发明名称 |
All-digital phase-locked loop for adaptively controlling closed-loop bandwidth, method of operating the same, and devices including the same |
摘要 |
A method of operating an all-digital phase-locked loop (ADPLL) includes detecting a phase change in a feedback signal of the ADPLL using a search window and controlling a closed-loop bandwidth of the ADPLL based on a detection result. The closed-loop bandwidth when the phase change is detected outside the search window is greater than the closed-loop bandwidth when the phase change is detected within the search window. |
申请公布号 |
US9077351(B2) |
申请公布日期 |
2015.07.07 |
申请号 |
US201414204251 |
申请日期 |
2014.03.11 |
申请人 |
SAMSUNG ELECTRONICS CO., LTD. |
发明人 |
Park Jae Jin;Jang Tae Kwang;Xing Nan;Liu Jen Lung |
分类号 |
H03L7/06;H03L7/085 |
主分类号 |
H03L7/06 |
代理机构 |
Sughrue Mion, PLLC |
代理人 |
Sughrue Mion, PLLC |
主权项 |
1. A method of operating an all-digital phase-locked loop (ADPLL), the method comprising:
detecting a phase change in a feedback signal of the ADPLL using a search window defined by two reference clock signals related to an input clock signal; and controlling a closed-loop bandwidth of the ADPLL based on a detection result of the detecting. |
地址 |
Suwon-si KR |