发明名称 Input/output cell design for thin gate oxide transistors with restricted poly gate orientation
摘要 An input/output circuit layout has a first section in which first transistors having a thicker gate oxide are located and a second section in which second transistors having a thinner gate oxide are located. Due to process technology constraints, the gates of all of the second transistors are oriented in a single common direction. The second section has a perimeter having a square shape including a first edge and a second edge adjacent to the first edge. First connection pins coupled to the second transistors are provided with an orientation that extends inwardly from and perpendicular to the first edge. Second connection pins coupled to the second transistors are provided with an orientation that extends inwardly from and perpendicular to said second edge. The square shape and presence of pins on adjacent first and second edges permits rotation of the second section to fit within different orientations of the layout.
申请公布号 US9075947(B2) 申请公布日期 2015.07.07
申请号 US201313911224 申请日期 2013.06.06
申请人 STMicroelectronics International N.V.;STMicroelectronics (Crolles 2) SAS 发明人 Kumar Manoj;Guillorit Jean;Dayani Navin Kumar
分类号 G06F17/50 主分类号 G06F17/50
代理机构 Gardere Wynne Sewell LLP 代理人 Gardere Wynne Sewell LLP
主权项 1. An integrated circuit including an input/output circuit, comprising: a first section in which first transistors powered from a higher supply voltage and having a first thickness gate oxide are located; a second section in which second transistors powered from a lower supply voltage and having a second thickness gate oxide, thinner than the first thickness, are located; wherein said second section includes at least one layout section having a square shaped perimeter including a first edge and a second edge adjacent to the first edge and including second transistors with transistor gates oriented in a single common direction; and wherein said at least one layout section further includes: a plurality of first connection pins coupled to said second transistors and which are oriented to extend inwardly from and perpendicular to said first edge; anda plurality of second connection pins coupled to said second transistors and which are oriented to extend inwardly from and perpendicular to said second edge.
地址 Amsterdam NL