Lock detector for phase-locked loop

摘要

A clock alignment detector described herein can detect alignment between clock signals within a defined margin of error, such as a defined margin of phase error. The margin of phase error can be varied to achieve various degrees of lock detection precision. Clock alignment detector can detect alignment between rising edges of the clock signals, falling edges of the clock signals, or both the rising and falling edges of the clock signals. The clock alignment detector can be implemented as a lock detector for a phase-locked loop that is configured to detect and maintain a phase relationship between a reference clock signal and a feedback clock signal, where the clock alignment detector detects alignment between the reference clock signal and the feedback clock signal.

主权项

1. A clock alignment detector configured to detect alignment between a first clock signal and a second clock signal, the clock alignment detector comprising:
an alignment state detector configured to generate a delayed alignment state signal that indicates an alignment state of the first clock signal and the second clock signal; a delayed alignment state detector configured to generate at least two alignment state signals that indicate a state of the delayed alignment state signal when triggered by edges of the first clock signal and the second clock signal; and an edge alignment state detector configured to generate an edge alignment state signal based on the at least two alignment state signals, wherein the edge alignment state signal indicates an alignment state of edges of the first clock signal and the second clock signal.