SPSRAM wrapper

摘要

Among other things, one or more techniques or systems for facilitating access operations to a single port memory device are provided. Multiple access operations to a single port memory device, such as a 6 transistor bitcell array of an SPSRAM, are performed during a single clock period of a system clock. In an embodiment, a wrapper controller initiates a first access operation during a first clock period of the system clock based upon a rising edge of the system clock. Responsive to receiving an operation complete signal during the first clock operation, the wrapper controller initiates a second access operation to the single port memory device during the first clock period. In this way, multi-port access functionality is implemented, such as in a serial manner to mitigate operation disturbs, for a single port memory device that occupies a relatively smaller area than a multi-port memory device for improved storage density.

主权项

1. A system for facilitating access operations to a single port memory device, comprising:
a wrapper controller configured to:
initiate a first access operation from a first port of a wrapper address component to a single port memory device during a first clock period;receive a clock reset signal from the single port memory device, the clock reset signal indicative of a completion of the first access operation; andinitiate a second access operation from a second port of the wrapper address component to the single port memory device during the first clock period responsive to receiving the clock reset signal.