发明名称 Storage system and method of controlling data transfer in storage system
摘要 An embodiment of the present invention is a storage system including a plurality of non-volatile storage devices for storing user data, and a controller for controlling data transfer between the plurality of non-volatile storage devices and a host. The controller includes a processor core circuit, a processor cache, and a primary storage device including a cache area for temporarily storing user data. The processor core circuit ascertains contents of a command received from the host. The processor core circuit ascertains a retention storage device of data to be transferred in the storage system in operations responsive to the command. The processor core circuit determines whether to transfer the data via the processor cache in the storage system, based on a type of the command and the ascertained retention storage device.
申请公布号 US9075729(B2) 申请公布日期 2015.07.07
申请号 US201213511888 申请日期 2012.05.16
申请人 Hitachi, Ltd. 发明人 Okada Naoya;Takada Masanori;Hirayama Hiroshi
分类号 G06F12/02;G06F12/08;G06F13/16 主分类号 G06F12/02
代理机构 Foley & Lardner LLP 代理人 Foley & Lardner LLP
主权项 1. A storage system comprising: a plurality of non-volatile storage devices for storing user data; and a controller for controlling data transfer between the plurality of non-volatile storage devices and a host, wherein the controller includes a processor core circuit, a processor cache, a data transfer circuit, a drive interface circuit, and a primary storage device including a cache area for temporarily storing user data; wherein the processor core circuit is configured to ascertain contents of a command received from the host; wherein the processor core circuit is configured to ascertain a retention storage device of data to be transferred in the storage system in operations responsive to the command; wherein the processor core circuit is configured to determine whether to transfer the data via the processor cache in the storage system, based on a type of the command and the ascertained retention storage device; wherein, when the determination is to transfer read data from a non-volatile storage device via the processor cache, the processor core circuit is configured to provide the drive interface circuit with an instruction to add hint information to the read data indicating transfer of data to the processor cache; wherein, when the drive interface circuit receives the instruction, the drive interface circuit is configured to add the hint information to the read data from the non-volatile storage device and transfer the read data with the hint information to the data transfer circuit; wherein the data transfer circuit is configured to transfer the read data to the processor cache in accordance with the hint information therewith; and wherein the processor core circuit is configured to determine, based on a type of the non-volatile storage device storing the read data, whether to flush the read data out from the processor cache to the cache area of the primary storage device after transferring the read data in the processor cache to the host.
地址 Tokyo JP