发明名称 Stacked semiconductor die with continuous conductive vias
摘要 A stacked semiconductor device includes a first, a second, a third, and a fourth semiconductor device. A first major surface of each of the first and second semiconductor devices which includes the active circuitry directly face each other, and a first major surface of each of the third and fourth semiconductor devices which includes the active circuitry directly face each other. A second major surface of the second semiconductor device directly faces a second major surface of the third semiconductor device. The stacked semiconductor device includes a plurality of continuous conductive vias, wherein each continuous conductive via extends from the second major surface of the first device, through the first device, second device, third device, and fourth device to the second major surface of the fourth device. Each of the semiconductor devices may include a beveled edge at the first major surface on at least one edge of the device.
申请公布号 US9076664(B2) 申请公布日期 2015.07.07
申请号 US201113268580 申请日期 2011.10.07
申请人 Freescale Semiconductor, Inc. 发明人 Pelley Perry H.;Hess Kevin J.;McShane Michael B.
分类号 H01L23/48;H01L25/065 主分类号 H01L23/48
代理机构 代理人
主权项 1. A stacked semiconductor device comprising: a first semiconductor device having a first major surface and a second major surface opposite the first major surface, the first major surface of the first semiconductor device with active circuitry; a second semiconductor device having a first major surface and a second major surface opposite the first major surface, the first major surface of the second semiconductor device with active circuitry; a third semiconductor device having a first major surface and a second major surface opposite the first major surface, the first major surface of the third semiconductor device with active circuitry; a fourth semiconductor device having a first major surface and a second major surface opposite the first major surface, the first major surface of the fourth semiconductor device with active circuitry, wherein: the first major surface of the first semiconductor device faces the first major surface of the second semiconductor device such that the first major surfaces of the first and second semiconductor devices are between the second major surfaces of the first and second semiconductor devices;the first major surface of the third semiconductor device faces the first major surface of the fourth semiconductor device such that the first major surfaces of the third and fourth semiconductor devices are between the second major surfaces of the third and fourth semiconductor devices; andthe second major surface of the second semiconductor device faces the second major surface of the third semiconductor device, such that the second major surfaces of the second and third semiconductor devices are between the first major surfaces of the second and third semiconductor devices; and at least one continuous conductive via, wherein each continuous conductive via of the at least one continuous conductive via extends from the second major surface of the first semiconductor device, through the first semiconductor device, second semiconductor device, and third semiconductor device; wherein each of the first, second, third, and fourth semiconductor devices comprises a beveled edge at the first major surface on at least one side of the semiconductor device, the first semiconductor device comprises a conductive plane which includes at least one protruding portion which is in contact with and extends from the at least one continuous conductive via onto the beveled edge of the first semiconductor device;the second semiconductor device comprises a conductive plane which includes at least one protruding portion which is in contact with and extends from the at least one continuous conductive via onto the beveled edge of the second semiconductor device;the third semiconductor device comprises a conductive plane which includes at least one protruding portion which is in contact with and extends from the at least one continuous conductive via onto the beveled edge of the third semiconductor device; andthe fourth semiconductor device comprises a conductive plane which includes at least one protruding portion which is in contact with and extends from the at least one continuous conductive via onto the beveled edge of the fourth semiconductor device.
地址 Austin TX US