| 发明名称 | Noise detection circuit, delay locked loop and duty cycle corrector including the same | ||
| 摘要 | A noise detection circuit includes a first delay unit suitable for delaying a periodic wave to output a delayed periodic wave, a first divider unit suitable for dividing the delayed periodic wave to output a first periodic wave, a second divider unit suitable for dividing the periodic wave to output a divided periodic wave, a second delay unit suitable for delaying the divided periodic wave to output a second periodic wave, and a detection unit suitable for comparing the first periodic wave with the second periodic wave and outputting a noise detection signal. | ||
| 申请公布号 | US9077438(B2) | 申请公布日期 | 2015.07.07 |
| 申请号 | US201314077933 | 申请日期 | 2013.11.12 |
| 申请人 | SK Hynix Inc. | 发明人 | Kang Tae-Wook;Na Kwang-Jin |
| 分类号 | H04B3/46 | 主分类号 | H04B3/46 |
| 代理机构 | IP & T Group LLP | 代理人 | IP & T Group LLP |
| 主权项 | 1. A noise detection circuit comprising: a first delay unit suitable for delaying a periodic wave to output a delayed periodic wave; a first divider unit suitable for dividing the delayed periodic wave to output a first periodic wave; a second divider unit suitable for dividing the periodic wave to output a divided periodic wave; a second delay unit suitable for delaying the divided periodic wave to output a second periodic wave; and a detection unit suitable for comparing the first periodic wave with the second periodic wave and outputting a noise detection signal. | ||
| 地址 | Gyeonggi-do KR | ||