Semiconductor memory device and method of testing the same

摘要

A semiconductor memory device comprises a first-supplied-voltage-supplying pad, a second-supplied-voltage-supplying pad, a data input/output pad, a memory body, a buffer circuit and an impedance-controlling circuit. A first supplied voltage is supplied to the memory body. A second supplied voltage is supplied to the buffer circuit. The impedance-controlling circuit controls an impedance of the buffer circuit on a side connected to the data input/output pad. The semiconductor memory device comprises a voltage-generating circuit generating a first inner voltage. The impedance-controlling circuit comprises a first P-channel transistor. A source terminal of the first P-channel transistor is connected to the first-supplied-voltage-supplying pad, and the first inner voltage generated from the voltage-generating circuit is selectively supplied to a gate terminal of the first P-channel transistor.

主权项

1. A semiconductor memory device, comprising:
a first pad to which a first supplied voltage is supplied; a second pad to which a second supplied voltage is supplied; a third pad; a memory body to which the first supplied voltage is supplied and memorizing data; a buffer circuit connected to the memory body and the third pad and to which the second supplied voltage is supplied; and an impedance-controlling circuit controlling an impedance of the buffer circuit, to which a first voltage is supplied as the first supplied voltage and to which one of the first voltage and a second voltage smaller than the first voltage is supplied as the second supplied voltage, wherein the semiconductor memory device comprises a voltage-generating circuit generating a first inner voltage from the first supplied voltage supplied via the first pad, as a replica element of transistors in a final stage of the buffer circuit, the impedance-controlling circuit comprises a first P-channel transistor at the final stage, and a source terminal of the first P-channel transistor is connected to the first pad, and the first inner voltage generated from the voltage-generating circuit is selectively supplied to a gate terminal of the first P-channel transistor.