| 发明名称 |
FRINGE CAPACITANCE REDUCTION FOR REPLACEMENT GATE CMOS |
| 摘要 |
A replacement metal gate transistor structure and method with thin silicon nitride sidewalls and with little or no high-k dielectric on the vertical sidewalls of the replacement gate transistor trench |
| 申请公布号 |
US2015187903(A1) |
申请公布日期 |
2015.07.02 |
| 申请号 |
US201414578722 |
申请日期 |
2014.12.22 |
| 申请人 |
Texas Instruments Incorporated |
发明人 |
Niimi Hiroaki;Nandakumar Mahalingam |
| 分类号 |
H01L29/51;H01L29/423;H01L29/78;H01L29/66;H01L21/28;H01L21/3213;H01L21/311;H01L21/321;H01L21/02;H01L29/49;H01L21/3105 |
主分类号 |
H01L29/51 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. An integrated circuit with a metal gate transistor comprising:
a replacement gate transistor trench; silicon nitride sidewalls with a thickness of less than about 0.3 nm on vertical sidewalls of the replacement gate transistor trench; high-k transistor gate dielectric with a thickness greater than about 1 nm on a bottom surface of the replacement gate transistor trench and wherein a thickness of the high-k transistor gate dielectric on the vertical sidewalls of the replacement gate transistor trench that is less than half the thickness on the bottom surface; and metal gate material covering the high-k transistor gate dielectric and filling the replacement gate transistor trench. |
| 地址 |
Dallas TX US |
