发明名称 |
Systems and Methods for Random Number Generation Using a Fractional Rate Clock |
摘要 |
Systems and methods are provided for generating a pseudo-random bit sequence at an output frequency using a clock signal operating at a first frequency that is lower than the output frequency. A first bit sequence of a particular type is generated using a clock signal operating at a first frequency. A second bit sequence is generated using the clock signal operating at the first frequency, where the second bit sequence is a delayed version of the first bit sequence. A delayed version of the first bit sequence is generated using the second bit sequence and another bit sequence, wherein the delayed version is delayed based on the particular type and a difference between the output frequency and the first frequency. The first bit sequence and the delayed version are combined to generate a pseudo-random bit sequence at the output frequency. |
申请公布号 |
US2015186235(A1) |
申请公布日期 |
2015.07.02 |
申请号 |
US201414577372 |
申请日期 |
2014.12.19 |
申请人 |
Semtech Canada Corporation |
发明人 |
Gorzkiewicz Dariusz |
分类号 |
G06F11/263 |
主分类号 |
G06F11/263 |
代理机构 |
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代理人 |
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主权项 |
1. A computer-implemented method of generating a pseudo-random bit sequence at an output frequency using a clock signal operating at a first frequency that is lower than the output frequency, comprising:
generating a first bit sequence of a particular type using a clock signal operating at a first frequency; generating a second bit sequence using the clock signal operating at the first frequency, wherein the second bit sequence is a delayed version of the first bit sequence; generating a delayed version of the first bit sequence using the second bit sequence and another bit sequence, wherein the delayed version is delayed based on the particular type and a difference between the output frequency and the first frequency; and combining the first bit sequence and the delayed version to generate a pseudo-random bit sequence at the output frequency. |
地址 |
Burlington CA |