发明名称 |
METHOD OF ANALYZING ERROR RATE IN SYSTEM-ON-CHIP |
摘要 |
In order to improve reliability of a system-on-chip (SoC) through fault tolerance verification, there is provided a method of analyzing an error rate in a system-on-chip (SoC) having at least one internal block obtained by interconnecting two or more gates, comprising: applying an input signal to an input terminal of a certain internal block; defining an input error rate of each gate of the internal block; and defining an output error rate of the internal block based on the input error rate of each gate and an error rate propagating to an output terminal. As a result, there is proposed a method of analyzing a change of the output error rate depending on the input error rate in a gate level in error model development necessary to design and verify a fault-tolerant SoC. Therefore, it is possible to analyze errors in each gate and formularize error rate information modeling including an input/output relationship between each gate of a digital circuit in a library form. |
申请公布号 |
US2015186199(A1) |
申请公布日期 |
2015.07.02 |
申请号 |
US201414585982 |
申请日期 |
2014.12.30 |
申请人 |
Foundation for Research & Business, Seoul National University of Science & Technology |
发明人 |
LEE Seung Eun;JEONG Yeong Seob;LEE Seong Mo |
分类号 |
G06F11/07;G06F11/22 |
主分类号 |
G06F11/07 |
代理机构 |
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代理人 |
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主权项 |
1. A method of analyzing an error rate in a system-on-chip (SoC) having at least one internal block obtained by interconnecting two or more gates, comprising:
applying an input signal to an input terminal of a certain internal block; defining an input error rate of each gate of the internal block; and defining an output error rate of the internal block based on the input error rate of each gate and an error rate propagating to an output terminal. |
地址 |
Seoul KR |