GATE DRIVING CIRCUIT AND DISPLAY DEVICE

摘要

The present disclosure discloses a gate driving circuit and a display device, to avoid power consumption arising from overlapping of voltages output by the output ends of gate drivers in the case that the gate driving circuit is configured with a plurality of clock signals. The gate driving circuit includes: a plurality of gate scan lines, and N stages of gate drivers connected in cascade. Each stage of gate drivers includes a reset end and an output end, which provides a gate scan signal to a corresponding gate scan lines. The output end of a m-th stage gate driver is connected provides a reset signal to the reset end of a (m−1)-th stage of gate drivers, N and m are positive integers, and m

主权项

1. A gate driving circuit, comprising:
a plurality of gate scan lines; and N stages of gate drivers connected in cascade, each stage of gate drivers comprising a reset end and an output end configured to provide a gate scan signal to a corresponding gate scan line; wherein, the output end of a m-th-stage gate driver is configured to provide a reset signal to a reset end of a (m−1)-th stage gate driver, N and m being positive integers, and m