发明名称 |
SINGLE COMPONENT CORRECTING ECC USING A REDUCIBLE POLYNOMIAL WITH GF(2) COEFFICIENTS |
摘要 |
A memory system is described that provides error detection and correction after a failure of a memory component. Each block of data in the memory system includes an array of bits logically organized into R rows and C columns, including C-2 data-bit columns containing data bits, a row check bit column including row-parity bits for each of the R rows in the block, and an inner check bit column including X inner check bits. The inner check bits are defined to cover bits in the array according to a set of check vectors, wherein each check vector is associated with a different bit in the array and is an element of Res(P), a residue system. Moreover, each column is stored in a different memory component, and the check bits are generated from the data bits to provide block-level detection and correction for both memory errors and a failed memory component. |
申请公布号 |
US2015188571(A1) |
申请公布日期 |
2015.07.02 |
申请号 |
US201414146496 |
申请日期 |
2014.01.02 |
申请人 |
Oracle International Corporation |
发明人 |
Loewenstein Paul N. |
分类号 |
H03M13/15 |
主分类号 |
H03M13/15 |
代理机构 |
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代理人 |
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主权项 |
1. A memory system that provides error detection and correction, comprising:
an access mechanism configured to access a block of data from the memory system, wherein each block of data in the memory system includes an array of bits logically organized into R rows and C columns, including C-2 data-bit columns containing data bits, a row check bit column including row-parity bits for each of the R rows in the block, and an inner check bit column including X inner check bits, which are defined to cover bits in the array in accordance with a set of check vectors, wherein each check vector is associated with a different bit in the array and is an element of Res(P), a residue system comprising a set of polynomials with GF(2) coefficients modulo a polynomial P with GF(2) coefficients, wherein each column is stored in a different memory component, and wherein the check bits are generated from the data bits to facilitate block-level detection and correction for errors generated in a memory component; and an error-detection circuit configured to,
examine a block of data retrieved by the access mechanism, anddetermine whether a memory component has generated an error based on the examination. |
地址 |
Redwood City CA US |