发明名称 THREE-DIMENSIONAL RESISTIVE MEMORY ARRAY
摘要 PROBLEM TO BE SOLVED: To provide a method for manufacturing a three-dimensional resistive memory array comprising a transistor selector in each cell.SOLUTION: The method comprises: forming a layer stack 102 including an isolating layer 104, a semiconductor layer 106, a gate insulating layer 108 and a conductive layer 110; forming a metal oxide layer 126 on inner side walls of trenches of a first type 114 formed in the layer stack 102; and forming conductive material of first and second types 128, 130 in the trenches of the first type 114 and a second type 116. The conductivity of an electrical path between a resistivity switching memory layer 310 formed by the metal oxide layer 126 and the conductive material of the first type 128 is controlled by a transistor device 302.
申请公布号 JP2015122478(A) 申请公布日期 2015.07.02
申请号 JP20140203418 申请日期 2014.10.01
申请人 IMEC 发明人 WOUTERS DIRK;GOURI SANKAR KAR
分类号 H01L27/105;H01L45/00 主分类号 H01L27/105
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