Instruction and Logic for Cache-Based Speculative Vectorization

摘要

A processor includes a decoder to decode an instruction, a scheduler to schedule the instruction, and an execution unit to execute the instruction. The instruction is to load a memory operation applicable to a quantity of addresses into an execution vector. The execution vector includes a plurality of vector positions for respective addressees. The instruction is further to evaluate, for a given address in the execution vector at a vector position, whether a cache indicates that a previous memory operation was performed at a higher vector position than the vector position of the given address. The instruction is also to determine, based on the evaluation whether the cache indicates that the previous memory operation was performed at a higher vector position than the vector position of the given address, whether the memory operation will cause a memory error.

主权项

1. A processor, comprising:
a decoder to decode a first instruction, the first instruction to:
load a memory operation applicable to a quantity of addresses into an execution vector, the execution vector including a plurality of vector positions for respective addressees;evaluate, for a given address in the execution vector at a vector position, whether a cache indicates that a previous memory operation was performed at a higher vector position than the vector position of the given address; anddetermine, based on the evaluation whether the cache indicates that the previous memory operation was performed at a higher vector position than the vector position of the given address, whether the memory operation will cause a memory error; a scheduler to schedule the first instruction; and an execution unit to execute the first instruction.