THREE DIMENSION PROGRAMMABLE RESISTIVE RANDOM ACCESSED MEMORY ARRAY WITH SHARED BITLINE AND METHOD

摘要

A method of forming a non-volatile memory device. The method forms a vertical stack of first polysilicon material and a second polysilicon material layer isolated by a dielectric material. The polysilicon material layers and the dielectric material are subjected to a first pattern and etch process to form a first wordline associated with a first switching device and a second wordline associated with a second switching device from the first polysilicon material layer, and a third wordline associated with a third switching device and a fourth wordline associated with a fourth switching device from the second polysilicon material. A via opening is formed to separate the first wordline from the second wordline and to separate the third wordline from the fourth wordline. An amorphous silicon switching material is deposited conformably overlying the via opening. A metal material fills the via opening and connects to a common bitline.

主权项

1. A method for forming a semiconductor device; comprising:
receiving a substrate having a surface region; disposing a first dielectric material overlying the surface region of the substrate; forming a first bottom electrode and a second bottom electrode overlying the first dielectric material, the first bottom electrode being associated with a first resistive switching device and the second bottom electrode being associated with a second resistive switching device; disposing a second dielectric material above the first bottom electrode and the second bottom electrode; forming a third bottom electrode and a fourth bottom electrode overlying the second dielectric material, the third bottom electrode being associated with a third resistive switching device and the fourth bottom electrode being associated with a fourth resistive switching device; forming a third dielectric material overlying the third bottom electrode and the fourth bottom electrode; forming a via in the third dielectric material and the second dielectric material, wherein the via exposes a sidewall of the first bottom electrode, a sidewall of the second bottom electrode, a sidewall of the third bottom electrode and a sidewall of the fourth bottom electrode; disposing a resistive switching material within the via structure, wherein a first portion of the resistive switching material is in electrical contact with the sidewall of the first bottom electrode, wherein a second portion of the resistive switching material is in electrical contact with the sidewall of the second bottom electrode, wherein a third portion of the resistive switching material is in electrical contact with the sidewall of the third bottom electrode, and wherein a fourth portion of the resistive switching material is in electrical contact with the sidewall of the fourth bottom electrode; disposing an active metal material within the via structure overlying the resistive switching material, wherein a first portion of the active metal material contacts the first portion of the resistive switching material, wherein a second portion of the active metal material contacts the second portion of the resistive switching material, wherein a third portion of the active metal material contacts the third portion of the resistive switching material, and wherein a fourth portion of the active metal material contacts the fourth portion of the resistive switching material; forming a top electrode coupling the active the metal material in the via structure.