Composite Structure for Gate Level Inter-Layer Dielectric

摘要

A method of forming an integrated circuit device includes forming dummy gates over a semiconductor substrate, depositing a first dielectric layer over the dummy gates, chemical mechanical polishing to recede the first dielectric layer to the height of the dummy gates, etching to recess the first dielectric layer below the height of the gates, depositing one or more additional dielectric layers over the first dielectric layer, and chemical mechanical polishing to recede the one or more additional dielectric layers to the height of the gates. The method provides integrated circuit devices having metal gate electrodes and an inter-level dielectric at the gate level that includes a capping layer. The capping layer resists etching and preserves the gate height through a replacement gate process.

主权项

1. An integrated circuit device, comprising:
a semiconductor body; a plurality of transistors over the semiconductor body, the transistors having metal gate electrodes of a height and spaced apart over the semiconductor body; a first dielectric structure comprising one or more dielectric layers and spanning a bulk of a width of the spaces between adjacent metal gate electrodes and having a thickness substantially equal to at least half the height of the metal gate electrodes, but rising to substantially less than the height of the metal gate electrodes; and a second dielectric structure comprising one or more dielectric layers and formed over the first dielectric structure, rising to approximately the height of the metal gate electrodes; wherein an uppermost portion of the first dielectric structure has a distinct composition from a lowermost portion of the second dielectric structure.