发明名称 PCB PROCESSING METHOD AND PCB
摘要 Disclosed are a PCB processing method and a PCB. The method comprises: conducting lamination processing on various layers of PCB sub-boards respectively forming a PCB according to PCB design requirements, and conducting hole drilling and electroplating on the PCB sub-boards of the uppermost layer of the PCB to form a via hole; and laminating the various layers of PCB sub-boards together to form the PCB, the via hole forming a blind hole used for installing a connector, and conducting hole drilling and electroplating on the formed PCB to form a through hole used for installing the connector, wherein the depth of the blind hole is greater than or equal to the length of a signal pin of the connector. By means of the technical solution of the present invention, the spacing between wafers among the lower layers of the PCBs can be doubled, so that the line outlet space between the wafers can be doubled.
申请公布号 WO2015096365(A1) 申请公布日期 2015.07.02
申请号 WO2014CN78052 申请日期 2014.05.21
申请人 ZTE CORPORATION 发明人 YI, BI;MA, FENGCHAO;REN, YONGHUI;XIONG, WANG;WANG, YINGXIN
分类号 H05K1/00;H05K3/04 主分类号 H05K1/00
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