IMPLANT PROFILING WITH RESIST

摘要

A process for forming at least two different doping levels at the surface of a wafer using one photo resist pattern and implantation process step. A resist layer is developed (but not baked) to form a first resist geometry and a plurality of sublithographic resist geometries. The resist layer is baked causing the sublithographic resist geometries to reflow into a continuous second resist geometry having a thickness less that the first resist geometry. A high energy implant implants dopants through the second resist geometry but not through the first resist geometry. A low energy implant is blocked by both the first and second resist geometries.

主权项

1. A process of forming an integrated circuit, comprising the steps:
forming a first photoresist implant blocking geometry on a wafer of the integrated circuit with a greater than or equal to minimum design rule width and with a first thickness; forming a plurality of sublithographic photoresist geometries and a plurality of sublithographic spaces between the sublithographic photoresist geometries on the wafer; performing a post develop bake at a temperature greater than the reflow temperature of the photo resist causing the sublithographic photoresist geometries and sublithographic spaces to reflow forming a second photoresist implant blocking geometry with a thickness that is less than the first thickness; implanting a first dopant with a high implant energy wherein the first dopant implant is blocked by the first photoresist implant blocking geometry, is implanted into the wafer through the second resist implant blocking geometry, and is implanted into the wafer where there is no photoresist geometry; and implanting a second dopant with a low energy wherein the second dopant implant is blocked by the first photoresist implant blocking geometry, is blocked by the second photoresist implant blocking geometry, and is implanted into the wafer where there is no photoresist geometry.