发明名称 Universal Error-Correction Circuit with Fault-Tolerant Nature, and Decoder and Triple Modular Redundancy Circuit That Apply It
摘要 A universal error-correction circuit with fault-tolerant nature includes an error-correction unit with fault-tolerant nature implemented by a logic gate, where digital input signals of the error-correction unit with fault-tolerant nature are separately I0, I1 . . . , I2k−1, and I2k, digital output signals of the error-correction unit with fault-tolerant nature are separately O0, O1, . . . , Ok−2, and Ok−1, and the digital input signals and the digital output signals belong to a set {0,1}, where k is a positive integer. The error-correction unit with fault-tolerant nature is configured to, when k=1, set O0=I0 if I0=I1, and O0=I2 otherwise; and when k>1, set Ok−1=I2k−1 if Ok−2=I2k−1, and Ok−1=I2k otherwise. Because a logical relationship between input and output is uniquely certain, the error-correction circuit with fault-tolerant nature may be implemented only by a logic gate.
申请公布号 US2015188580(A1) 申请公布日期 2015.07.02
申请号 US201414581570 申请日期 2014.12.23
申请人 Huawei Technologies Co., Ltd. 发明人 Tang Yangyang;Zhang Chen-Xiong
分类号 H03M13/00;H03M13/11;H03M13/27 主分类号 H03M13/00
代理机构 代理人
主权项 1. A universal error-correction circuit with fault-tolerant nature, comprising: an error-correction unit with fault-tolerant nature implemented by a logic gate, wherein digital input signals of the error-correction unit with fault-tolerant nature are separately I0, I1 . . . , I2k−1, and I2k, wherein digital output signals of the error-correction unit with fault-tolerant nature are separately O0, O1 . . . , Ok−2, and Ok−1, wherein the digital input signals and the digital output signals belong to a set {0,1}, wherein k is a positive integer, and wherein the error-correction unit with fault-tolerant nature is configured to: set O0=I0 when k=1 and I0=I1;set O0=I2 when I0 is not equal to I1;set Ok−1=I2k−1 when k>1 and Ok−2=I2k−1; andset Ok−1=I2k when Ok−1 is not equal to I2k−1.
地址 Shenzhen CN