发明名称 TRANSMISSION CIRCUIT AND TRANSMISSION/RECEPTION CIRCUIT
摘要 PROBLEM TO BE SOLVED: To match latency and synchronization release timing among channels.SOLUTION: A transmission circuit, which has a plurality of channels which can operate with different clocks and transmits transmission data to a reception circuit from each of the channels, includes a synchronization signal generation circuit for generating mutually synchronized, same frequency synchronization signals for each of the channels on the basis of each of clocks for the plurality of channels. Each channel includes a FIFO for outputting a digital signal, synchronized to a first clock defined for each channel, and a synchronization signal with synchronizing to a second clock defined for each channel, a control interface for signal processing and outputting a digital signal outputted by the FIFO according to the second clock, and a transmission part for transmitting a signal outputted by the control interface to the reception circuit. The control interface of each channel starts signal processing for a digital signal according to a synchronization signal outputted by the FIFO.
申请公布号 JP2015122574(A) 申请公布日期 2015.07.02
申请号 JP20130264329 申请日期 2013.12.20
申请人 ASAHI KASEI ELECTRONICS CO LTD 发明人 DAIMON TAKAYUKI
分类号 H04L7/04;H04L7/00 主分类号 H04L7/04
代理机构 代理人
主权项
地址