| 主权项 |
1. A method for facilitating operation of a processor core coupled to a first instruction memory containing executable instructions, a first data memory containing data, a second instruction memory, a second data memory, a third data memory and a third instruction memory, the method comprising:
examining instructions being filled from the second instruction memory to the third instruction memory, extracting instruction information containing at least branch information and generating a stride length of a base register value corresponding to each data access instruction; creating a plurality of tracks based on the extracted instruction information; filling at least one or more instructions that are likely to be executed by the processor core based on one or more tracks from the plurality of tracks from the first instruction memory to the second instruction memory; filling at least one or more instructions based on one or more tracks from the plurality of tracks from the second instruction memory to the third instruction memory before the processor core executes the instructions, such that the processor core fetches the at least one or more instructions from the third memory; calculating a possible data access address of a data access instruction to be executed next time based on the stride length of the base register value; and filling the data in the first data memory to the third data memory based on the calculated possible data access addresses of the data access instruction to be executed. |
