HIGH MOBILITY TRANSISTORS

摘要

An integrated circuit containing an n-channel finFET and a p-channel finFET is formed by forming a first polarity fin epitaxial layer for a first polarity finFET, and subsequently forming a hard mask which exposes an area for a second, opposite, polarity fin epitaxial layer for a second polarity finFET. The second polarity fin epitaxial layer is formed in the area exposed by the hard mask. A fin mask defines the first polarity fin and second polarity fin areas, and a subsequent fin etch forms the respective fins. A layer of isolation dielectric material is formed over the substrate and fins. The layer of isolation dielectric material is planarized down to the fins. The layer of isolation dielectric material is recessed so that the fins extend at least 10 nanometers above the layer of isolation dielectric material. Gate dielectric layers and gates are formed over the fins.

主权项

1. An integrated circuit, comprising:
a substrate comprising a semiconductor material extending to a top surface of said substrate, said semiconductor material comprising crystalline silicon; an n-channel fin field effect transistor (finFET), comprising:
a first buffer disposed on said semiconductor material of said substrate at said top surface of said substrate, said first buffer comprising germanium-containing semiconductor material;an n-channel fin disposed on said first buffer, said n-channel fin comprising semiconductor material different from silicon;a first gate dielectric layer disposed over said n-channel fin; anda first gate disposed over said first gate dielectric layer; a p-channel finFET, comprising:
a p-channel fin disposed over said substrate, said p-channel fin comprising semiconductor material different from silicon and different from said semiconductor material of said n-channel fin;a second gate dielectric layer disposed over said p-channel fin; anda second gate disposed over said second gate dielectric layer; and an isolation dielectric layer disposed over said substrate around said first buffer and said n-channel fin and around said p-channel fin, such that said n-channel fin and said p-channel fin extend at least 10 nanometers above said isolation dielectric layer.