| 摘要 |
A charge pump that uses a control unit of a chip to adjust the on/off status of power switches and capacitor boost switches of a change-over switch set, enabling input voltage to be boosted by selected capacitors to the desired voltage level subject to conduction and cutoff of selected transistors, and therefore a predetermined voltage level of output voltage can be provided to an internal working circuit of an electronic apparatus without changing the circuit layout of the chip and the package substrate that is packaged on the chip, and thus, the chip and the package substrate simply need to be verified once, eliminating further verification procedure and time prior to vending and saving much the cost. |
| 主权项 |
1. A charge pump, comprising a chip and a package substrate packaged on said chip and installed in a circuit board comprising an input voltage, N−1 capacitors and a voltage stabilizer capacitor, the capacitors of said circuit board being adapted for storing and boosting said input voltage to provide an output voltage, wherein
said chip comprises:
a clock generator for generating a first clock pulse and a reversed second clock pulse;a first clock terminal electrically connected to said clock generator for receiving said first clock pulse;a second clock terminal electrically connected to said clock generator for receiving said second clock pulse;a transistor set comprising N transistors numbered 1st through Nth, said N being ≧4, the collectors of said transistors being respectively electrically connected to the respective bases thereof, the emitters of 1st through N−1 transistors being respectively electrically connected to the junctions between the collectors and bases of the 2nd through Nth transistors;a change-over switch set comprising N−1 power switches and N−2 capacitor boost switches, respective one ends of the 1st through (N−1)th power switches being respectively electrically connected to junctions between the collectors and bases of the 1st through (N−1)th transistors, respective one ends of the 1st through (N−2)th capacitor boost switches being respectively electrically connected to junctions between the collectors and bases of the 2nd through (N−1)th transistors;a control unit electrically connected to respective one ends of the 1st through (N−1)th power switches and respective one ends of the 1st through (N−2)th capacitor boost switches;an input terminal set comprising N input terminals numbered from the 1st through Nth, the first input terminal being electrically connected to respective opposite ends of the 1st through (N−1)th power switches, the 2nd through (N−1)th input terminals being respectively electrically connected to respective opposite ends of the 1st through (N−2)th capacitor boost switches, the Nth input terminal being electrically connected to the junction between the collector and base of the Nth transistor; andan output terminal electrically connected to the emitter of the Nth transistor; said package substrate comprises:
a first clock pin electrically connected to said first clock terminal and electrically connected to respective one ends of odd number capacitors of said circuit board;a second clock pin electrically connected to said second clock terminal and electrically connected to respective one ends of even number capacitors of said circuit board;an external pin set comprising N external pins numbered from 1st through Nth, the 1st external pin being electrically connected to said first input terminal and said input voltage, the 2nd through Nth external pins being respectively electrically connected to 2nd through Nth input terminals and respective opposite ends of the 1st through (N−1)th capacitors; anda power output pin electrically connected to said output terminal of said chip. |
