DOUBLE-SIDED SEGMENTED LINE ARCHITECTURE IN 3D INTEGRATION

摘要

Embodiments of the present invention relate generally to electronic components such as semiconductor wafers and more particularly, to a double-sided three-dimensional (3D) hierarchal architecture scheme for multiple semiconductor wafers using an arrangement of through silicon vias (TSVs) and backside wiring. In an embodiment a first word line architecture may be formed on a front side of an IC chip and connected to a second word line architecture formed on a back side of the IC chip through intra-wafer, TSVs, thereby relocating required wiring to the back side of the IC chip.

主权项

1. A method, comprising:
forming one or more intra-wafer through substrate vias (TSVs) extending from a front side of an integrated circuit (IC) chip to a back side of the IC chip; forming a local architecture in a front side wiring layer of the IC chip, the local architecture having one or more local features electrically connected to the one or more intra-wafer TSVs; and forming a global architecture in a back side wiring layer of the IC chip, the global architecture connecting to the one or more intra-wafer TSVs and electrically coupling the one or more local features together, wherein a thickness of an individual wire in the global architecture is n times larger than a thickness of an individual wire in the local architecture, with the value of n being selected to reduce the number of repeaters/re-buffers required for distributing global signals, and n varying between approximately 8 and approximately 10.