METHOD WITH SYSTEM AND PROGRAM PRODUCT FOR PRIORITIZING CLOCK DOMAINS FOR TESTING OF INTEGRATED CIRCUIT DESIGNS

摘要

The present disclosure generally provides for a method of prioritizing clock domains for testing an integrated circuit (IC) design. The method can include: assigning each of a plurality of multi-tested clock domains (MTCDs) and a plurality of test experiments (TEs) to one of a plurality of speed priority groups (SPGs), wherein the assigning includes: creating a new SPG having a priority value of n+1, wherein n represents the number of previously created SPGs; assigning a first MTCD corresponding to at least two of the plurality of TEs, the first MTCD not being previously assigned to an SPG, to the new SPG; and assigning each TE corresponding to the first MTCD, each of the assigned TEs not being previously assigned to an SPG, to the new SPG; and performing each of the plurality of TEs on the IC design in order from lowest priority value to highest priority value.

主权项

1. A method of prioritizing clock domains for testing an integrated circuit (IC) design, the method comprising:
assigning each of a plurality of multi-tested clock domains (MTCDs) and a plurality of test experiments (TEs) to one of a plurality of speed priority groups (SPGs), wherein the assigning includes:
creating a new SPG having a priority value of n+1, wherein n represents the number of previously created SPGs;assigning a first MTCD corresponding to at least two of the plurality of TEs, the first MTCD not being previously assigned to an SPG, to the new SPG; andassigning each TE corresponding to the first MTCD, each of the assigned TEs not being previously assigned to an SPG, to the new SPG; and performing each of the plurality of TEs on the IC design in order from lowest priority value to highest priority value.