HANDLING SLOWER SCAN OUTPUTS AT OPTIMAL FREQUENCY

摘要

An embodiment provides a circuit for testing an integrated circuit. The circuit includes a scan compression architecture driven by a scan clock and generates M scan outputs, where M is an integer. A clock divider is configured to divide the scan clock by k to generate k number of phase-shifted scan clocks, where k is an integer. A packing logic is coupled to the scan compression architecture and generates kM slow scan outputs in response to the M scan outputs and the k number of phase shifted scan clocks. The packing logic further includes M number of packing elements and each packing element of the M number of packing elements receives a scan output of the M scan outputs. Each packing element includes k number of flip-flops and each flip-flop of the k number of flip-flops in a packing element receives a scan output of the M scan outputs. Each flip-flop receives a phase-shifted scan clock of the k number of phase-shifted scan clocks, such that each flip-flop generates a slow scan output of the kM slow scan outputs in response to the scan output and the phase-shifted scan clock.

主权项

1. A circuit comprising:
a scan compression architecture driven by a scan clock and configured to generate M scan outputs, where M is an integer; a clock divider configured to divide the scan clock by k to generate k number of phase-shifted scan clocks, where k is an integer; and a packing logic coupled to the scan compression architecture and configured to generate kM slow scan outputs in response to the M scan outputs and the k number of phase shifted scan clocks, wherein the packing logic comprises:
M number of packing elements, each packing element of the M number of packing elements configured to receive a scan output of the M scan outputs; andk number of flip-flops in each packing element, each flip-flop of the k number of flip-flops in a packing element configured to receive a scan output of the M scan outputs and configured to receive a phase-shifted scan clock of the k number of phase-shifted scan clocks, such that each flip-flop generates a slow scan output of the kM slow scan outputs in response to the scan output and the phase-shifted scan clock.