| 发明名称 |
Data Coherency Model and Protocol at Cluster Level |
| 摘要 |
An apparatus for providing data coherency is described herein. The apparatus includes a global persistent memory. The global persistent memory is accessed using a protocol that includes input/output (I/O) semantics and memory semantics. The apparatus also includes a reflected memory region. The reflected memory region is a portion of the global persistent memory, and each node of a plurality of nodes maps the reflected memory region into a space that is not cacheable. Further, the apparatus includes a semaphore memory. The semaphore memory provides a hardware assist for enforced data coherency. |
| 申请公布号 |
US2015186057(A1) |
申请公布日期 |
2015.07.02 |
| 申请号 |
US201314142733 |
申请日期 |
2013.12.27 |
| 申请人 |
Das Sharma Debendra;Kumar Mohan J.;Fleischer Balin T. |
发明人 |
Das Sharma Debendra;Kumar Mohan J.;Fleischer Balin T. |
| 分类号 |
G06F3/06;G06F11/20;G06F13/32 |
主分类号 |
G06F3/06 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. An apparatus for providing data coherency, comprising:
a global persistent memory, wherein the global persistent memory is accessed using a protocol that includes input/output (I/O) semantics and memory semantics; a reflected memory region, wherein the reflected memory region is a portion of the global persistent memory, and each node of a plurality of nodes maps the reflected memory region into a space that is not cacheable; and a semaphore memory, wherein the semaphore memory provides a hardware assist for enforced data coherency. |
| 地址 |
Saratoga CA US |
